Hardware for spike-coded neural networks utilizing hybrid CMOS non-volatile technologies

DESCRIPTION

The major challenge of this Chair of Excellence is to pave the way for the third generation of neural networks, namely spiking neural networks (SNNs).

SNNs draw inspiration from biological systems, whose computations are 3 to 6 orders of magnitude more energy-efficient than current dedicated digital neural network implementations. The goal is to bridge this gap using massively parallel, configurable, non-von Neumann spike-based architectures—based on highly dense, intertwined computation and storage elements—that harness self-learning and self-organizing capabilities.

This chair draws on a multidisciplinary team, which is essential for achieving the right combination of learning algorithms, large-scale, energy-efficient accelerators, and industrial applications.

ACTIVITIES

The Chair has hired two PhD students to work on coding and learning strategies on one hand, and on architecture definition and circuit design on the other. This software-hardware co-design approach is key to achieving significant gains in energy efficiency.

Work is currently underway to determine, among all possible AI applications, which ones will benefit the most from spike coding.

CHAIR EVENTS

A. Valentian, “Choosing the right combination of technology, design, and tools is key to successful Edge AI solutions,” Keynote Talk, ValleyML AI Expo 2020 Conference Series, Virtual event, October 2020

F. Petrot, L. Anghel, L. Andrade, “State of the Art: Hardware-Accelerated Neural Networks,” Oral Presentation, Applied Machine Learning Days @ EFFL, January 27, 2020

SELECTED LIST OF PUBLICATIONS

  • L. Anghel, “Binarized Ensemble Neural Networks Based on Spintronic Devices”—November 2021, IEEE/ACM International Symposium on Nanoscale Architectures.

  • A. Valentian, “Hardware Approaches to Energy-Efficient AI,” Invited Presentation, Planet Tech’Care, Workshop—AI and Energy Consumption, February 2021.

  • A. Valentian, W. Weinreich, “AI Chips for the Edge—New Computing Architectures for Low-Power AI,” EU-Japan Symposium on Semiconductors, Virtual event, April 2021.

  • A. Valentian, “How to Design Power-Efficient Hardware for AI—The Bio-Inspired Approach,” Tiny ML Talks, Webcast, September 2021.

  • V. Cinçon, Elena Ioana Vatajelu, Lorena Anghel, Philippe Galy, “From 1.8V to 0.19V Voltage Bias on Analog Spiking Neurons in 28nm UTBB FD-SOI Technology,” IEEE EUROSOI-ULIS Conference, September 2020

  • A. Valentian, “Choosing the right combination of technology, design, and tools is key to successful Edge AI solutions,” Keynote Talk, ValleyML AI Expo 2020 Conference Series, October 2020.

  • A. Valentian, F. Rummens, E. Vianello, T. Mesquida, C. Lecat-Mathieu de Boissac, O. Bichler, C. Reita, “Fully Integrated Spiking Neural Network with Analog Neurons and RRAM Synapses,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2019.

  • M. Bouvier, A. Valentian, T. Mesquida, F. Rummens, M. Reyboz, E. Vianello, E. Beigné, “Spiking Neural Networks Hardware Implementations and Challenges: a Survey,” ACM Journal on Emerging Technologies in Computing Systems (ACM JETC), Special Issue on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning, August 2019
Published on September 30, 2026
Updated on October 14, 2026