Interdisciplinary Institute in Artificial Intelligence

DESCRIPTION

The Digital Hardware AI Architecture chair focuses on the integration of highly energy-efficient hardware and software architectures to implement AI tasks in general, and deep neural networks in particular.

The main challenges involve the tight integration of AI accelerators into software-intensive systems, taking into account a wide range of non-functional requirements: low to very low power consumption, ease of use as a system-level coprocessor, reproducibility of results, real-time and low-latency computations, virtualization of AI functions for deployment on diverse execution platforms, compatibility with academic or industrial machine learning frameworks, etc.

ACTIVITIES

Cooperation between the University of Salerno, Italy, STMicroelectronics, Agrate, IT, and the Chair to work on tiny binary neural networks.
A CIFRE PhD program has begun in collaboration with STMicroelectronics, Crolles, on an ultra-low-power TPU.
The concept of a TCAM-based ternary neural network accelerator is under investigation, with the goal of building a highly efficient, very low-power matrix multiplication engine.
Compression of table-based implementations of complex functions (exponentiation, logarithms, trigonometric functions, etc.) for FPGAs is being studied as a solution to maximize FPGA utilization for convolution and activation function computations.
Finally, an FPGA backend for PyTorch is being developed to facilitate the exploration of hardware designs for network architectures.

CHAIR EVENTS

Invited talk at the Applied Machine Learning Days in Lausanne, Switzerland, January 25–29, 2020.

SELECTED LIST OF PUBLICATIONS 

• Liliana Lilibeth Andrade Porras, Thomas Baumela, Frédéric Pétrot, D. Briand, Olivier Bichler et al. An Efficient Deep Learning Approach for Fault Detection in the Semiconductor Industry. ADTC 2021 - European Nanoelectronics Applications Design & Technology Conference, June 2021, Grenoble, France.


• Tiago Trevisan Jost, Yves Durand, Christian Fabre, Albert Cohen, Frédéric Pétrot. "Seamless Compiler Integration of Variable-Precision Floating-Point Arithmetic." International Symposium on Code Generation and Optimization (CGO 2021), February 2021, Atlanta, United States.


• M. Badaroux, Saverio Miroddi, Frédéric Pétrot. “To Pin or Not to Pin: Asserting the Scalability of QEMU’s Parallel Implementation.” 24th Euromicro Conference on Digital System Design (Euromicro DSD/SEAA 2021), September 2021, Palermo, Italy. pp. 238–245.


• M. Badaroux, Frédéric Pétrot. "Support for Arbitrary and Variable-Precision Floating-Point Arithmetic in Dynamic Binary Translation." 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Jan. 2021, Tokyo (virtual event), Japan.


• B.J. Fernandez-Mesa, Liliana Lilibeth Andrade Porras, Frédéric Pétrot. Simulation of Ideally Switched Circuits in SystemC. Asia and South Pacific Design Automation Conference (ASP-DAC 2021), January 2021, Tokyo, Japan.


• B.J. Fernandez-Mesa, Liliana Lilibeth Andrade Porras, Frédéric Pétrot. “Synchronization of Continuous-Time and Discrete-Event Simulation in SystemC.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2021, 40 (7), pp. 1450–1463.


• L. Bonicel, R. Bohrer, B. Leprettre, Frédéric Pétrot, Frédéric Rousseau. Component-Based Framework for Designing and Validating Asynchronous Algorithms for Electrical Measurement and Protection. 4th IEEE International Conference on Industrial Cyber-Physical Systems (ICPS 2021), May 2021, Victoria, BC, Canada.


• Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groleat, Frédéric Pétrot. “Toward Agile Hardware Designs with Chisel: A Network Use Case.” IEEE Design & Test, IEEE, 2021.


• Low-Power Tiny Binary Neural Network with Improved Accuracy in Human Recognition Systems. Euromicro DSD Conference, August 26–28, 2020.